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cy8cled16 ez-color? hb led controller cypress semiconductor corporation ?198 champion court?san jose , ca 95134-1709?408-943-2600 document number: 001-13105 rev. ** revised june 12, 2007 features hb led controller ? configurable dimmers support up to 16 independent led channels ? 8-32 bits of resolution per channel ? dynamic reconfiguration enables led controller plus other features; battery charging, motor control? visual embedded design, psoc express ? led based express drivers ? binning compensation ? temperature feedback ?dmx512 prism modulation technology ? reduces radiated emi ? reduces low frequency blinking powerful harvard architecture processor ? m8c processor speeds to 24 mhz ? 3.0 to 5.25v operating voltage ? operating voltages down to 1.0v using on-chip switch mode pump (smp) ? industrial temperature range: -40c to +85c programmable pin configurations ? 25 ma sink on all gpio ? pull up, pull down, high z, strong, or open drain drive modes on all gpio ? up to eight analog inputs on gpio ? configurable interrupt on all gpio advanced peripherals (psoc blocks) ? 16 digital psoc blocks provide: ? 8 to 32-bit timers, counters, and pwms ? up to 2 full-duplex uart ? multiple spi ? masters or slaves ? connectable to all gpio pins ? 12 rail-to-rail analog psoc blocks provide: ? up to 14-bit adcs ? up to 9-bit dacs ? programmable gain amplifiers ? programmable filters and comparators ? complex peripherals by combining blocks flexible on-chip memory ? 32k flash program storage 50,000 erase/write cycles ? 2k sram data storage ? in-system serial programming (issp) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash complete development tools ? free development software ? psoc designer? ? psoc express? ? full-featured, in-cir cuit emulator and programmer ? full speed emulation ? complex breakpoint structure ? 128 kbytes trace memory ez-color hb led controller preliminary data sheet
cy8cled16 document number: 001-13105 rev. ** page 2 of 39 overview digital system sram 2k interrupt controller sleep and watchdog multiple clock sources (includes imo, ilo, pll, and eco) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 32k digital block array two multiply accums. switch mode pump internal voltage ref. digital clocks por and lvd system resets decimator system resources analog system analog block array analog ref. analog input muxing i c 2 port 7 port 6 port 5 port 4 port 3 port 2 port 1 port 0 analog drivers system bus block diagram
cy8cled16 document number: 001-13105 rev. ** page 3 of 39 ez-color functional overview cypress' ez-color family of de vices offers the ideal control solution for high brightness led applications requiring intel- ligent dimming control. ez-color devices combine the power and flexibility of psoc (programmable system-on-chip?); with cypress' prism (precise illumination signal modulation) modulation technology providing lighting designers a fully customizable and integrated lighting solution platform. the ez-color family supports up to 16 independent led channels with up to 32 bits of resolution per channel, enabling lighting designers the flexibility to choose the led array size and color quality. psoc express software, with lighting specific drivers, can significantly cut development time and simplify implementation of fixed color points through temperature and led binning compensation. ez-color's virtually limitless analog and digital customization allow fo r simple integration of features in addition to intelligent lighting, such as battery charging, image stabilization, and motor control during the development process. these features, along with cypress' best-in-class quality and design support, make ez-color the ideal choice for intelligent hb led control applications. target applications lcd backlight large signs general lighting architectural lighting camera/cell phone flash flashlights the psoc core the psoc core is a powerful engine that supports a rich feature set. the core includes a cpu, me mory, clocks, and configurable gpio (general purpose io). the m8c cpu core is a powerful processor with speeds up to 48 mhz, providing a four mips 8-bi t harvard architecture micropro- cessor. the cpu utilizes an interr upt controller with 25 vectors, to simplify programming of real time embedded events. program execution is timed and protected using the included sleep and watch dog timers (wdt). memory encompasses 32 kb of fl ash for program storage, 2 kb of sram for data storage, and up to 2 kb of eeprom emulated using the flash. program flash ut ilizes four protection levels on blocks of 64 bytes, a llowing customized software ip protection. the ez-color family incorporates flexible internal clock gener- ators, including a 24 mhz imo (internal main oscillator) accurate to 2.5% over temperature and voltage. the 24 mhz imo can also be doubled to 48 mhz for use by the digital system. a low power 32 khz ilo (internal low speed oscillator) is provided for the sleep timer and wdt. if crystal accuracy is desired, the eco (32.768 khz external crystal oscillator) is available for use as a real time clock (rtc) and can optionally generate a crystal-accurate 24 mhz system cl ock using a pll. the clocks, together with programmable clock dividers (as a system resource), provide the flexibility to integrate almost any timing requirement into the ez-color device. ez-color gpios provide connection to the cpu, digital and analog resources of the device. each pin?s drive mode may be selected from eight options, allowing great flexibility in external interfacing. every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. the digital system the digital system is composed of 16 digital psoc blocks. each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit per ipherals, which are called user module references. digital peripheral configura- tions include those listed below. prism (8 to 32 bit) pwms (8 to 32 bit) pwms with dead band (8 to 32 bit) counters (8 to 32 bit) timers (8 to 32 bit) uart 8 bit with selectable parity (up to 4) spi master and slave (up to 4 each) i2c slave and multi-master (1 available as a system resource) cyclical redundancy checker/generator (8 to 32 bit) irda (up to 4) generators (8 to 32 bit) the digital blocks can be connected to any gpio through a series of global buses that can route any signal to any pin. the buses also allow for signal multiplexing and for performing logic operations. this configurability frees your designs from the constraints of a fixed peripheral controller. digital blocks are provided in ro ws of four, where the number of blocks varies by ez-color device family. this allows you the optimum choice of system resource s for your application. family resources are shown in the table titled ez-color device charac- teristics on page 4.
cy8cled16 document number: 001-13105 rev. ** page 4 of 39 figure 1. digital system block diagram the analog system the analog system is composed of 12 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. analog peripherals are very flexible and can be customized to support spec ific application requirements. some of the more common ez-color analog functions (most available as user modules) are listed below. analog-to-digital converters (up to 4, with 6- to 14-bit resolution, selectable as incremental, delta sigma, and sar) filters (2, 4, 6, or 8 pole band-pass, low-pass, and notch) amplifiers (up to 4, with selectable gain to 48x) instrumentation amplifiers (up to 2, with selectable gain to 93x) comparators (up to 4, with 16 selectable thresholds) dacs (up to 4, with 6- to 9-bit resolution) multiplying dacs (up to 4, with 6- to 9-bit resolution) high current output drivers (four with 40 ma drive as a core resource) 1.3v reference (as a system resource) dtmf dialer modulators correlators peak detectors many other topologies possible analog blocks are provided in co lumns of three, which includes one ct (continuous time) and two sc (switched capacitor) blocks, as shown in the figure below. digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 1 dbb10 dbb11 dcb12 dcb13 row input configuration 4 4 row output configuration row input configuration row output configuration row 2 dbb20 dbb21 dcb22 dcb23 4 4 row 0 dbb00 dbb01 dcb02 dcb03 4 4 row input configuration row output configuration row 3 dbb30 dbb31 dcb32 dcb33 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 7 port 6 port 5 port 4 port 3 port 2 port 1 port 0
cy8cled16 document number: 001-13105 rev. ** page 5 of 39 figure 2. analog system block diagram additional system resources system resources, some of wh ich have been previously listed, provide additional capability useful to complete systems. resources include a multiplier, decimator, switch mode pump, low voltage detection, and power on reset. statements describing the merits of each system resource are presented below. digital clock dividers provide three customizable clock frequencies for use in applications. the clocks can be routed to both the digital and analog systems. additional clocks can be generated using digital psoc blocks as clock dividers. multiply accumulate (mac) provi des fast 8-bit multiplier with 32-bit accumulate, to assist in general math and digital filters. the decimator provides a custom hardware filter for digital signal, processing applications in cluding the creation of delta sigma adcs. the i2c module provides 100 and 400 khz communication over two wires. slave, master, and multi-master modes are all supported. low voltage detection (lvd) interrupts can signal the appli- cation of falling voltage levels, while the advanced por (power on reset) circuit eliminates the need for a system supervisor. an internal 1.3 voltage reference provides an absolute reference for the analog system, including adcs and dacs. an integrated switch mode pump (smp) generates normal operating voltages from a single 1.2v battery cell, providing a low cost boost converter. acb00 acb01 block array array input configuration aci1[1:0] aci2[1:0] acb02 acb03 asc12 asd13 asd22 asc23 asd20 aci0[1:0] aci3[1:0] p0[6] p0[4] p0[2] p0[0] p2[2] p2[0] p2[6] p2[4] refin agndin p0[7] p0[5] p0[3] p0[1] p2[3] p2[1] reference generators agndin refin bandgap refhi reflo agnd asd11 asc21 asc10 interface to digital system m8c interface (address bus, data bus, etc.) analog reference
cy8cled16 document number: 001-13105 rev. ** page 6 of 39 ez-color device characteristics depending on your ez-color device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6 , or 4 analog blocks. the following tabl e lists the resources available for specific ez-c olor device groups. th e device covered by thi s data sheet is shown in the highlighted row of the table. getting started the quickest path to understandi ng the ez-color silicon is by reading this data sheet and using psoc express to create hb led applications. this data sheet is an overview of the ez-color integrated circuit and presents specific pin, register, and electrical specifications. for up-to-date ordering, packaging, and electrical specification information, reference the latest device data sheets on the web at http://www.cypress.com/ez-color. development kits development kits are available from the following distributors: digi-key, avnet, arrow, and future. the cypress online store at http://www.onfulfillment.com/cypressstore/ contains devel- opment kits, c compilers, and all accessories for psoc devel- opment. click on ez-color to view a current list of available items. technical training modules free psoc technical training modules are available for users new to psoc. training modules cover designing, debugging, advanced analog, capsense, and hb led. go to http://www.cypre ss.com/techtrain . consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant, go to the following cypress support web site: http://www.cypress.com/support/cypros.cfm . technical support psoc application engineers take pride in fast and accurate response. they can be reached with a 4-hour guaranteed response at http://www.cypress.c om/support/login.cfm . application notes a long list of application notes will assist you in every aspect of your design effort. to view the psoc application notes, go to the http://www.cypress.com web site and select application notes under the design resources list located in the center of the web page. application notes are listed by date by default. table 1. ez-color device characteristics psoc part number led channels digital io digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size capsense cy8cled04 4 56 1 4 48 2 2 6 1k 16k yes cy8cled08 8 44 2 8 12 4 4 12 256 bytes 16k no cy8cled16 16 64 4 16 12 4 4 12 2k 32k no
cy8cled16 document number: 001-13105 rev. ** page 7 of 39 development tools psoc express is a high-level design tool for creating embedded systems with devices using cy press's psoc mixed-signal technology. with psoc express you create a complete embedded solution including all necessary on-chip peripherals, block configuration, interrupt handling and application software without writing a single line of assembly or c code. psoc express solves design problems the way you think about the system: select input and ou tput devices based upon system require- ments. add a communications interface and define its interface to system (using registers). define when and how an output device changes state based upon any and all other system devices. based upon the design, automatically select one or more psoc mixed-signal controllers that match system requirements. figure 3. psoc express psoc express subsystems express editor the express editor allows you to create designs visually by dragging and dropping inputs, outputs, communication inter- faces, and other design elements, and then describing the logic that controls them. project manager the project manager allows you to work with your applications and projects in psoc express. a psoc express application is a top level container for projects and their associated files. each project contains a design that uses a single psoc device. an application can contain multiple pr ojects so if you are creating an application that uses multiple psoc devices you can keep all of the projects together in a single application. most of the files associated with a project ar e automatically generated by psoc express duri ng the build process, but you can make changes directly to the custom.c and custom.h files and also add your own custom code to the project in the project manager. application editor the application editor allows you to edit custom.c and custom.h as well as any c or assembly language source code that you add to your project. with psoc express you can create application software without writing a single line of assembly or c code, but you have a full featured application ed itor at your finger tips if you want it. build manager the build manager gives you the ability to build the application software, assign pins, and generate the data sheet, schematic, and bom for your project. board monitor the board monitor is a debugging tool designed to be used while attached to a prototype board through a communication interface that allows you to monitor changes in the various design elements in real time. the default communication for the board monitor is i 2 c. it uses the cy3240-i2usb i 2 c to usb bridge debugging/communica- tion kit. tuners a tuner is a visual interface for the board monitor that allows you to view the performance of the hb led drivers on your test board while your program is running, and manually override val- ues and see the results. hardware tools in-circuit emulator a low cost, high functionality ice (in-circuit emulator) is available for development support. this hardware has the capability to progra m single devices. the emulator consists of a base unit that connects to the pc by way of the usb port. the base unit is universal and will operate with all psoc devices. emulation pods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full speed (24 mhz) operation. i 2 c to usb bridge the i 2 c to usb bridge is a quick and easy link from any design or application?s i 2 c bus to a pc via usb for design testing, debugging and communication.
cy8cled16 document number: 001-13105 rev. ** page 8 of 39 document conventions acronyms used the following table lists the acronyms that are used in this document. units of measure a units of measure table is locat ed in the electrical specifications section. table 7 on page 15 lists all the abbreviations used to measure the psoc devices. numeric naming hexidecimal numbers are represented with all letters in uppercase with an appended lowercas e ?h? (for example, ?14h? or ?3ah?). hexidecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (e.g., 01010100b? or ?01000011b?). numbers not indicated by an ?h?, ?b?, or 0x are decimal. acronym description ac alternating current adc analog-to-digital converter api application programming interface cpu central processing unit ct continuous time dac digital-to-analog converter dc direct current eco external crystal oscillator eeprom electrically erasable programmable read-only memory fsr full scale range gpio general purpose io gui graphical user interface hbm human body model ice in-circuit emulator ilo internal low speed oscillator imo internal main oscillator io input/output ipor imprecise power on reset lsb least-significant bit lvd low voltage detect msb most-significant bit pc program counter pll phase-locked loop por power on reset ppor precision power on reset psoc? programmable system-on-chip? pwm pulse width modulator sc switched capacitor slimo slow imo smp switch mode pump sram static random access memory
cy8cled16 document number: 001-13105 rev. ** page 9 of 39 pin information pinouts the cy8cled16 device is available in three packages which are li sted and illustrated in the following tables. every port pin (l abeled with a ?p?) is capable of digital io. however, vss, vdd, smp, and xres are not capable of digital io. 28-pin part pinout table 2. 28-pin part pinout (ssop) pin no. type pin name description 28-pin device digital analog 1 io i p0[7] analog column mux input. 2 io io p0[5] analog column mux input and column output. 3 io io p0[3] analog column mux input and column output. 4 io i p0[1] analog column mux input. 5 io p2[7] 6 io p2[5] 7 io i p2[3] direct switched capacitor block input. 8 io i p2[1] direct switched capacitor block input. 9 power smp switch mode pump (smp) connection to external components required. 10 io p1[7] i2c serial clock (scl). 11 io p1[5] i2c serial data (sda). 12 io p1[3] 13 io p1[1] crystal (xtalin), i2c serial clock (scl), issp-sclk*. 14 power vss ground connection. 15 io p1[0] crystal (xtalout), i2c serial data (sda), issp-sdata*. 16 io p1[2] 17 io p1[4] optional external clock input (extclk). 18 io p1[6] 19 input xres active high external reset with internal pull down. 20 io i p2[0] direct switched capacitor block input. 21 io i p2[2] direct switched capacitor block input. 22 io p2[4] external analog ground (agnd). 23 io p2[6] external voltage reference (vref). 24 io i p0[0] analog column mux input. 25 io io p0[2] analog column mux input and column output. 26 io io p0[4] analog column mux input and column output. 27 io i p0[6] analog column mux input. 28 power vdd supply voltage. legend : a = analog, i = input, and o = output. * these are the issp pins, which are not high z at por (power on reset). a, i, p0[7] a, io, p0[5] a, io, p0[3] a, i, p0[1] p2[7] p2[5] a, i, p2[3] a, i, p2[1] smp i2c scl, p1[7] i2c sda, p1[5] p1[3] i2c scl, xtalin, p1[1] vss vdd p0[6], a, i p0[4], a, io p0[2], a, io p0[0], a, i p2[6], external vref p2[4], external agnd p2[2], a, i p2[0], a, i xres p1[6] p1[4], extclk p1[2] p1[0], xtalout, i2c sda ssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
cy8cled16 document number: 001-13105 rev. ** page 10 of 39 48-pin part pinouts table 3. 48-pin part pinout (ssop) pin no. type pin name description 48-pin device digital analog 1 io i p0[7] analog column mux input. 2 io io p0[5] analog column mux input and column output. 3 io io p0[3] analog column mux input and column output. 4 io i p0[1] analog column mux input. 5 io p2[7] 6 io p2[5] 7 io i p2[3] direct switched capacitor block input. 8 io i p2[1] direct switched capacitor block input. 9 io p4[7] 10 io p4[5] 11 io p4[3] 12 io p4[1] 13 power smp switch mode pump (smp) connection to external components required. 14 io p3[7] 15 io p3[5] 16 io p3[3] 17 io p3[1] 18 io p5[3] 19 io p5[1] 20 io p1[7] i2c serial clock (scl). 21 io p1[5] i2c serial data (sda). 22 io p1[3] 23 io p1[1] crystal (xtalin), i2c serial clock (scl), issp-sclk*. 24 power vss ground connection. 25 io p1[0] crystal (xtalout), i2c serial data (sda), issp-sdata*. 26 io p1[2] 27 io p1[4] optional external clock input (extclk). 28 io p1[6] 29 io p5[0] 30 io p5[2] 31 io p3[0] 32 io p3[2] 33 io p3[4] 34 io p3[6] 35 input xres active high external reset with internal pull down. 36 io p4[0] 37 io p4[2] 38 io p4[4] 39 io p4[6] 40 io i p2[0] direct switched capacitor block input. 41 io i p2[2] direct switched capacitor block input. 42 io p2[4] external analog ground (agnd). 43 io p2[6] external voltage reference (vref). 44 io i p0[0] analog column mux input. 45 io io p0[2] analog column mux input and column output. 46 io io p0[4] analog column mux input and column output. 47 io i p0[6] analog column mux input. 48 power vdd supply voltage. legend : a = analog, i = input, and o = output. * these are the issp pins, which are not high z at por (power on reset). ssop a, i, p0[7] vdd a, io, p0[5] p0[6], a, i a, io, p0[3] p0[2], a, io a, i, p0[1] p0[4], a, io p2[7] p0[0], a, i p2[5] p2[6], external vref a, i, p2[3] p2[4], external agnd a, i, p2[1] p2[2], a, i p4[7] p2[0], a, i p4[5] p4[6] p4[3] p4[4] p4[1] p4[2] smp p4[0] p3[7] xres p3[5] p3[6] p3[3] p3[4] p3[1] p3[2] p5[3] p3[0] p5[1] p5[2] i2c scl, p1[7] p5[0] i2c sda, p1[5] p1[6] p1[3] p1[4], extclk i2c scl, xtalin, p1[1] p1[2] vss p1[0], xtalout, i2c sda 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 43 44 42 40 41 39 38 37 36 35 33 34 32 31 30 29 28 27 26 25
cy8cled16 document number: 001-13105 rev. ** page 11 of 39 table 4. 48-pin part pinout (qfn**) pin no. type pin name description 48-pin psoc device digital analog 1 io i p2[3] direct switched capacitor block input. 2 io i p2[1] direct switched capacitor block input. 3 io p4[7] 4 io p4[5] 5 io p4[3] 6 io p4[1] 7 power smp switch mode pump (smp) connection to external components required. 8 io p3[7] 9 io p3[5] 10 io p3[3] 11 io p3[1] 12 io p5[3] 13 io p5[1] 14 io p1[7] i2c serial clock (scl). 15 io p1[5] i2c serial data (sda). 16 io p1[3] 17 io p1[1] crystal (xtalin), i2c serial clock (scl), issp-sclk*. 18 power vss ground connection. 19 io p1[0] crystal (xtalout), i2c serial data (sda), issp-sdata*. 20 io p1[2] 21 io p1[4] optional external clock input (extclk). 22 io p1[6] 23 io p5[0] 24 io p5[2] 25 io p3[0] 26 io p3[2] 27 io p3[4] 28 io p3[6] 29 input xres active high external reset with internal pull down. 30 io p4[0] 31 io p4[2] 32 io p4[4] 33 io p4[6] 34 io i p2[0] direct switched capacitor block input. 35 io i p2[2] direct switched capacitor block input. 36 io p2[4] external analog ground (agnd). 37 io p2[6] external voltage reference (vref). 38 io i p0[0] analog column mux input. 39 io io p0[2] analog column mux input and column output. 40 io io p0[4] analog column mux input and column output. 41 io i p0[6] analog column mux input. 42 power vdd supply voltage. 43 io i p0[7] analog column mux input. 44 io io p0[5] analog column mux input and column output. 45 io io p0[3] analog column mux input and column output. mlf (top view) p2[5] p2[7] p0[1], a, i p0[3], a, io p0[5], a, io p0[7], a, i vdd p0[6], a, i p0[4], a, io p0[2], a, io p0[0], a, i p2[6], external vref 10 11 12 a, i, p2[3] a, i, p2[1] p4[7] p4[5] p4[3] p4[1] smp p3[7] p3[5] p3[3] p3[1] p5[3] 35 34 33 32 31 30 29 28 27 26 25 36 48 47 46 45 44 43 42 41 40 39 38 37 p2[2], a, i p2[0], a, i p4[6] p4[4] p4[2] p4[0] xres p3[6] p3[4] p3[2] p3[0] p2[4], external agnd 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 p5[1] i2c scl, p1[7] i2c sda, p1[5] p1[3] i2c scl, xtalin, p1[1] vss i2c sda, xtalout, p1[0] p1[2] extclk, p1[4] p1[6] p5[0] p5[2]
cy8cled16 document number: 001-13105 rev. ** page 12 of 39 register reference register conventions abbreviations used the register conventions specific to this section are listed in the following table. register mapping tables this chapter lists the registers of the cy8cled16 ez-color device. the device has a total register address space of 512 bytes. the register space is referred to as io space and is divided into two banks. the xoi bit in the flag register (cpu_f) determines which bank the user is currently in. when the xoi bit is set the user is in bank 1. note in the following register mapping tables, blank fields are reserved and should not be accessed. 46 io i p0[1] analog column mux input. 47 io p2[7] 48 io p2[5] legend : a = analog, i = input, and o = output. * these are the issp pins, which are not high z at por (power on reset). ** the qfn package has a center pad t hat must be connected to ground (vss). table 4. 48-pin part pinout (qfn**) convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific table 5. register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) acces name addr (0,hex) acces prt0dr 00 rw dbb20dr0 40 # asc10cr0 80 rw rdi2ri c0 rw prt0ie 01 rw dbb20dr1 41 w asc10cr1 81 rw rdi2syn c1 rw prt0gs 02 rw dbb20dr2 42 rw asc10cr2 82 rw rdi2is c2 rw prt0dm2 03 rw dbb20cr0 43 # asc10cr3 83 rw rdi2lt0 c3 rw prt1dr 04 rw dbb21dr0 44 # asd11cr0 84 rw rdi2lt1 c4 rw prt1ie 05 rw dbb21dr1 45 w asd11cr1 85 rw rdi2ro0 c5 rw prt1gs 06 rw dbb21dr2 46 rw asd11cr2 86 rw rdi2ro1 c6 rw prt1dm2 07 rw dbb21cr0 47 # asd11cr3 87 rw c7 prt2dr 08 rw dcb22dr0 48 # asc12cr0 88 rw rdi3ri c8 rw prt2ie 09 rw dcb22dr1 49 w asc12cr1 89 rw rdi3syn c9 rw prt2gs 0a rw dcb22dr2 4a rw asc12cr2 8a rw rdi3is ca rw prt2dm2 0b rw dcb22cr0 4b # asc12cr3 8b rw rdi3lt0 cb rw prt3dr 0c rw dcb23dr0 4c # asd13cr0 8c rw rdi3lt1 cc rw prt3ie 0d rw dcb23dr1 4d w asd13cr1 8d rw rdi3ro0 cd rw prt3gs 0e rw dcb23dr2 4e rw asd13cr2 8e rw rdi3ro1 ce rw prt3dm2 0f rw dcb23cr0 4f # asd13cr3 8f rw cf prt4dr 10 rw dbb30dr0 50 # asd20cr0 90 rw cur_pp d0 rw prt4ie 11 rw dbb30dr1 51 w asd20cr1 91 rw stk_pp d1 rw prt4gs 12 rw dbb30dr2 52 rw asd20cr2 92 rw d2 prt4dm2 13 rw dbb30cr0 53 # asd20cr3 93 rw idx_pp d3 rw prt5dr 14 rw dbb31dr0 54 # asc21cr0 94 rw mvr_pp d4 rw prt5ie 15 rw dbb31dr1 55 w asc21cr1 95 rw mvw_pp d5 rw prt5gs 16 rw dbb31dr2 56 rw asc21cr2 96 rw i2c_cfg d6 rw prt5dm2 17 rw dbb31cr0 57 # asc21cr3 97 rw i2c_scr d7 # prt6dr 18 rw dcb32dr0 58 # asd22cr0 98 rw i2c_dr d8 rw prt6ie 19 rw dcb32dr1 59 w asd22cr1 99 rw i2c_mscr d9 # prt6gs 1a rw dcb32dr2 5a rw asd22cr2 9a rw int_clr0 da rw prt6dm2 1b rw dcb32cr0 5b # asd22cr3 9b rw int_clr1 db rw prt7dr 1c rw dcb33dr0 5c # asc23cr0 9c rw int_clr2 dc rw prt7ie 1d rw dcb33dr1 5d w asc23cr1 9d rw int_clr3 dd rw blank fields are reserved and should no t be accessed. # access is bit specific.
cy8cled16 document number: 001-13105 rev. ** page 13 of 39 prt7gs 1e rw dcb33dr2 5e rw asc23cr2 9e rw int_msk3 de rw prt7dm2 1f rw dcb33cr0 5f # asc23cr3 9f rw int_msk2 df rw dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w 61 a1 int_msk1 e1 rw dbb00dr2 22 rw 62 a2 int_vc e2 rc dbb00cr0 23 # arf_cr 63 rw a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 dec_dh e4 rc dbb01dr1 25 w asy_cr 65 # a5 dec_dl e5 rc dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # 67 a7 dec_cr1 e7 rw dcb02dr0 28 # 68 mul1_x a8 w mul0_x e8 w dcb02dr1 29 w 69 mul1_y a9 w mul0_y e9 w dcb02dr2 2a rw 6a mul1_dh aa r mul0_dh ea r dcb02cr0 2b # 6b mul1_dl ab r mul0_dl eb r dcb03dr0 2c # tmp_dr0 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcb03dr1 2d w tmp_dr1 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcb03dr2 2e rw tmp_dr2 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcb03cr0 2f # tmp_dr3 6f rw acc1_dr2 af rw acc0_dr2 ef rw dbb10dr0 30 # acb00cr3 70 rw rdi0ri b0 rw f0 dbb10dr1 31 w acb00cr0 71 rw rdi0syn b1 rw f1 dbb10dr2 32 rw acb00cr1 72 rw rdi0is b2 rw f2 dbb10cr0 33 # acb00cr2 73 rw rdi0lt0 b3 rw f3 dbb11dr0 34 # acb01cr3 74 rw rdi0lt1 b4 rw f4 dbb11dr1 35 w acb01cr0 75 rw rdi0ro0 b5 rw f5 dbb11dr2 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 dbb11cr0 37 # acb01cr2 77 rw b7 cpu_f f7 rl dcb12dr0 38 # acb02cr3 78 rw rdi1ri b8 rw f8 dcb12dr1 39 w acb02cr0 79 rw rdi1syn b9 rw f9 dcb12dr2 3a rw acb02cr1 7a rw rdi1is ba rw fa dcb12cr0 3b # acb02cr2 7b rw rdi1lt0 bb rw fb dcb13dr0 3c # acb03cr3 7c rw rdi1lt1 bc rw fc dcb13dr1 3d w acb03cr0 7d rw rdi1ro0 bd rw fd dcb13dr2 3e rw acb03cr1 7e rw rdi1ro1 be rw cpu_scr1 fe # dcb13cr0 3f # acb03cr2 7f rw bf cpu_scr0 ff # table 6. register map bank 1 table: configuration space name addr(1,hex) access name addr(1,hex) access name addr(1,hex) acces s name addr(1,hex) acces s prt0dm0 00 rw dbb20fn 40 rw asc10cr0 80 rw rdi2ri c0 rw prt0dm1 01 rw dbb20in 41 rw asc10cr1 81 rw rdi2syn c1 rw prt0ic0 02 rw dbb20ou 42 rw asc10cr2 82 rw rdi2is c2 rw prt0ic1 03 rw 43 asc10cr3 83 rw rdi2lt0 c3 rw prt1dm0 04 rw dbb21fn 44 rw asd11cr0 84 rw rdi2lt1 c4 rw prt1dm1 05 rw dbb21in 45 rw asd11cr1 85 rw rdi2ro0 c5 rw prt1ic0 06 rw dbb21ou 46 rw asd11cr2 86 rw rdi2ro1 c6 rw prt1ic1 07 rw 47 asd11cr3 87 rw c7 prt2dm0 08 rw dcb22fn 48 rw asc12cr0 88 rw rdi3ri c8 rw prt2dm1 09 rw dcb22in 49 rw asc12cr1 89 rw rdi3syn c9 rw prt2ic0 0a rw dcb22ou 4a rw asc12cr2 8a rw rdi3is ca rw prt2ic1 0b rw 4b asc12cr3 8b rw rdi3lt0 cb rw prt3dm0 0c rw dcb23fn 4c rw asd13cr0 8c rw rdi3lt1 cc rw prt3dm1 0d rw dcb23in 4d rw asd13cr1 8d rw rdi3ro0 cd rw prt3ic0 0e rw dcb23ou 4e rw asd13cr2 8e rw rdi3ro1 ce rw prt3ic1 0f rw 4f asd13cr3 8f rw cf prt4dm0 10 rw dbb30fn 50 rw asd20cr0 90 rw gdi_o_in d0 rw prt4dm1 11 rw dbb30in 51 rw asd20cr1 91 rw gdi_e_in d1 rw prt4ic0 12 rw dbb30ou 52 rw asd20cr2 92 rw gdi_o_ou d2 rw prt4ic1 13 rw 53 asd20cr3 93 rw gdi_e_ou d3 rw prt5dm0 14 rw dbb31fn 54 rw asc21cr0 94 rw d4 prt5dm1 15 rw dbb31in 55 rw asc21cr1 95 rw d5 prt5ic0 16 rw dbb31ou 56 rw asc21cr2 96 rw d6 prt5ic1 17 rw 57 asc21cr3 97 rw d7 blank fields are reserved and should no t be accessed. # access is bit specific. table 5. register map bank 0 table: user space (continued) name addr (0,hex) access name addr (0,hex) access name addr (0,hex) acces name addr (0,hex) acces blank fields are reserved and should no t be accessed. # access is bit specific.
cy8cled16 document number: 001-13105 rev. ** page 14 of 39 prt6dm0 18 rw dcb32fn 58 rw asd22cr0 98 rw d8 prt6dm1 19 rw dcb32in 59 rw asd22cr1 99 rw d9 prt6ic0 1a rw dcb32ou 5a rw asd22cr2 9a rw da prt6ic1 1b rw 5b asd22cr3 9b rw db prt7dm0 1c rw dcb33fn 5c rw asc23cr0 9c rw dc prt7dm1 1d rw dcb33in 5d rw asc23cr1 9d rw osc_go_en dd rw prt7ic0 1e rw dcb33ou 5e rw asc23cr2 9e rw osc_cr4 de rw prt7ic1 1f rw 5f asc23cr3 9f rw osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw 64 a4 vlt_cmp e4 r dbb01in 25 rw 65 a5 e5 dbb01ou 26 rw amd_cr1 66 rw a6 e6 27 alt_cr0 67 rw a7 dec_cr2 e7 rw dcb02fn 28 rw alt_cr1 68 rw a8 imo_tr e8 w dcb02in 29 rw clk_cr2 69 rw a9 ilo_tr e9 w dcb02ou 2a rw 6a aa bdg_tr ea rw 2b 6b ab eco_tr eb w dcb03fn 2c rw tmp_dr0 6c rw ac ec dcb03in 2d rw tmp_dr1 6d rw ad ed dcb03ou 2e rw tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef dbb10fn 30 rw acb00cr3 70 rw rdi0ri b0 rw f0 dbb10in 31 rw acb00cr0 71 rw rdi0syn b1 rw f1 dbb10ou 32 rw acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 dbb11fn 34 rw acb01cr3 74 rw rdi0lt1 b4 rw f4 dbb11in 35 rw acb01cr0 75 rw rdi0ro0 b5 rw f5 dbb11ou 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 77 rw b7 cpu_f f7 rl dcb12fn 38 rw acb02cr3 78 rw rdi1ri b8 rw f8 dcb12in 39 rw acb02cr0 79 rw rdi1syn b9 rw f9 dcb12ou 3a rw acb02cr1 7a rw rdi1is ba rw fls_pr1 fa rw 3b acb02cr2 7b rw rdi1lt0 bb rw fb dcb13fn 3c rw acb03cr3 7c rw rdi1lt1 bc rw fc dcb13in 3d rw acb03cr0 7d rw rdi1ro0 bd rw fd dcb13ou 3e rw acb03cr1 7e rw rdi1ro1 be rw cpu_scr1 fe # 3f acb03cr2 7f rw bf cpu_scr0 ff # table 6. register map bank 1 ta ble: configuration space (continued) name addr(1,hex) access name addr(1,hex) access name addr(1,hex) acces s name addr(1,hex) acces s blank fields are reserved and should no t be accessed. # access is bit specific.
cy8cled16 document number: 001-13105 rev. ** page 15 of 39 electrical specifications this chapter presents the dc and ac electrical specifications of the cy8cled16 ez-color device. fo r the most up to date electri cal specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypre ss.com/ez-color. specifications are valid for -40 o c t a 85 o c and t j 100 o c, except where noted. refer to tabl e 23 for the electrical specifications on the internal main oscillator (imo) using slimo mode. figure 4. voltage versus cpu frequency, and imo frequency trim options the following table lists the units of me asure that are used in this chapter. table 7. units of measure symbol unit of measure symbol unit of measure o c degree celsius w microwatts db decibels ma milli-ampere ff femto farad ms milli-second hz hertz mv milli-volts kb 1024 bytes na nanoampere kbit 1024 bits ns nanosecond khz kilohertz nv nanovolts k kilohm ohm mhz megahertz pa picoampere m megaohm pf picofarad a microampere pp peak-to-peak f microfarad ppm parts per million h microhenry ps picosecond s microsecond sps samples per second v microvolts sigma: one standard deviation vrms microvolts root-mean-square v volts 5.25 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency vdd voltage 5.25 4.75 3.00 93 khz 12 mhz 24 mhz imo frequency vdd voltage 3.60 6 mhz slimo mode = 0 slimo mode=0 slimo mode=1 v a l i d o p e r a t i n g re g i o n slimo mode=1 slimo mode=0
cy8cled16 document number: 001-13105 rev. ** page 16 of 39 absolute maximum ratings operating temperature table 8. absolute maximum ratings symbol description min typ max units notes t stg storage temperature -55 25 +100 o c higher storage temperatures will reduce data retention time. recommended storage temper- ature is +25 o c 25 o c. extended duration stor- age temperatures above 65 o c will degrade reliability. t a ambient temperature with power applied -40 ? +85 o c vdd supply voltage on vdd relative to vss -0.5 ? +6.0 v v io dc input voltage vss - 0.5 ? vdd + 0.5 v v ioz dc voltage applied to tri-state vss - 0.5 ? vdd + 0.5 v i mio maximum current into any port pin -25 ? +50 ma i maio maximum current into any port pin configured as analog driver -50 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd. lu latch-up current ? ? 200 ma table 9. operat ing temperature symbol description min typ max units notes t a ambient temperature -40 ? +85 o c t j junction temperature -40 ? +100 o c the temperature rise from ambient to junction is package specific. see ?thermal impedances per package? on page 36. the user must limit the power consumption to comply with this requirement.
cy8cled16 document number: 001-13105 rev. ** page 17 of 39 dc electrical characteristics dc chip-level specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. dc general purpose io specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 10. dc chip-level specifications symbol description min typ max units notes vdd supply voltage 3.00 ? 5.25 v see dc por and lvd specifications, table 3-15 on page 27. i dd supply current ? 8 14 ma conditions are 5.0v, t a = 25 o c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 0.366 khz. i dd3 supply current ? 5 9 ma conditions are vdd = 3.3v, t a = 25 o c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 0.366 khz. i ddp supply current when imo = 6 mhz using slimo mode. ? 2 3 ma conditions are vdd = 3.3v, t a = 25 o c, cpu = 0.75 mhz, sysclk doubler disabled, vc1 = 0.375 mhz, vc2 = 23.44 khz, vc3 = 0.09 khz. i sb sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. ? 3 10 a conditions are with internal slow speed oscilla- tor, vdd = 3.3v, -40 o c t a 55 o c. i sbh sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. ? 4 25 a conditions are with internal slow speed oscilla- tor, vdd = 3.3v, 55 o c < t a 85 o c. i sbxtl sleep (mode) current with por, lvd, sleep timer, wdt, internal slow oscillator, and 32 khz crystal oscillator active. ? 4 12 a conditions are with properly loaded, 1 w max, 32.768 khz crystal. vdd = 3.3v, -40 o c t a 55 o c. i sbxtlh sleep (mode) current with por, lvd, sleep timer, wdt, and 32 khz crystal oscillator active. ? 5 27 a conditions are with properly loaded, 1 w max, 32.768 khz crystal. vdd = 3.3v, 55 o c < t a 85 o c. v ref reference voltage (bandgap) 1.28 1.3 1.32 v trimmed for appropriate vdd. table 11. dc gpio specifications symbol description min typ max units notes r pu pull up resistor 4 5.6 8 k r pd pull down resistor 4 5.6 8 k v oh high output level vdd - 1.0 ? ? v ioh = 10 ma, vdd = 4.75 to 5.25v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 80 ma maximum combined ioh budget. v ol low output level ? ? 0.75 v iol = 25 ma, vdd = 4.75 to 5.25v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 150 ma maximum combined iol budget. v il input low level ? ? 0.8 v vdd = 3.0 to 5.25. v ih input high level 2.1 ? v vdd = 3.0 to 5.25. v h input hysterisis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25 o c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25 o c.
cy8cled16 document number: 001-13105 rev. ** page 18 of 39 dc operational amplifier specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. the operational amplifier is a component of both the analog co ntinuous time psoc blocks and the analog switched capacitor psoc blocks. the guaranteed specifications are meas ured in the analog continuous time psoc bl ock. typical parameters apply to 5v at 25 c and are for design guidance only. table 12. 5v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ?1.6 1.3 1.2 10 8 7.5 mv mv mv ? ? tcv osoa average input offset voltage drift ? 7.0 35.0 v/ o c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 o c. v cmoa common mode voltage range. all cases, except high- est. power = high, opamp bias = high 0.0 ? vdd vdd - 0.5 v v 0.5 ? cmrr oa common mode rejection ratio 60 ? ? db g oloa open loop gain 80 ? ? db v ohighoa high output voltage swing (internal signals) vdd - .01 ? ? v v olowoa low output voltage swing (internal signals) ? ? 0.1 v i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 150 300 600 1200 2400 4600 200 400 800 1600 3200 6400 a a a a a a psrr oa supply voltage rejection ratio 67 80 ? db vss vin (vdd - 2.25) or (vdd - 1.25v) vin vdd . table 13. 3.3v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) power = low, opamp bias = high power = medium, opamp bias = high high power is 5 volts only ? ? 1.65 1.32 10 8 mv mv tcv osoa average input offset voltage drift ? 7.0 35.0 v/ o c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 o c. v cmoa common mode voltage range 0 ? vdd v cmrr oa common mode rejection ratio 60 ? ? db g oloa open loop gain 80 ? ? db v ohighoa high output voltage swing (internal signals) vdd - .01 ? ? v v olowoa low output voltage swing (internal signals) ? ? .01 v
cy8cled16 document number: 001-13105 rev. ** page 19 of 39 dc low power comparator specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v at 25 c and are for design guidance only. dc analog output bu ffer specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 150 300 600 1200 2400 ? 200 400 800 1600 3200 ? a a a a a not allowed psrr oa supply voltage rejection ratio 54 80 ? db vss vin (vdd - 2.25) or (vdd - 1.25v) vin vdd table 13. 3.3v dc operational am plifier specifications (continued) table 14. dc low power comparator specifications symbol description min typ max units notes v reflpc low power comparator (lpc) reference voltage range 0.2 ? vdd - 1 v i slpc lpc supply current ? 10 40 a v oslpc lpc voltage offset ? 2.5 30 mv table 15. 5v dc analog output buffer specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? v/c v cmob common-mode input voltage range 0.5 ? vdd - 1.0 v r outob output resistance power = low power = high ? ? ? ? 1 1 v ohighob high output voltage swing (load = 32 ohms to vdd/2) power = low power = high 0.5 x vdd + 1.3 0.5 x vdd + 1.3 ? ? ? ? v v v olowob low output voltage swing (load = 32 ohms to vdd/2) power = low power = high ? ? ? ? 0.5 x vdd - 1.3 0.5 x vdd - 1.3 v v i sob supply current including bias cell (no load) power = low power = high ? ? 1.1 2.6 2 5 ma ma psrr ob supply voltage rejection ratio 40 64 ? db
cy8cled16 document number: 001-13105 rev. ** page 20 of 39 dc switch mode pump specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 16. 3.3v dc analog output buffer specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? v/c v cmob common-mode input voltage range 0.5 - vdd - 1.0 v r outob output resistance power = low power = high ? ? ? ? 10 10 v ohighob high output voltage swing (load = 1k ohms to vdd/2) power = low power = high 0.5 x vdd + 1.0 0.5 x vdd + 1.0 ? ? ? ? v v v olowob low output voltage swing (load = 1k ohms to vdd/2) power = low power = high ? ? ? ? 0.5 x vdd - 1.0 0.5 x vdd - 1.0 v v i sob supply current including bias cell (no load) power = low power = high ? 0.8 2.0 1 5 ma ma psrr ob supply voltage rejection ratio 60 64 ? db table 17. dc switch mode pump (smp) specifications symbol description min typ max units notes v pump 5v 5v output voltage at vdd from pump 4.75 5.0 5.25 v configuration of footnote. a average, neglecting ripple. smp trip voltage is set to 5.0v. v pump 3v 3v output voltage at vdd from pump 3.00 3.25 3.60 v configuration of footnote. a average, neglecting ripple. smp trip voltage is set to 3.25v. i pump available output current v bat = 1.5v, v pump = 3.25v v bat = 1.8v, v pump = 5.0v 8 5 ? ? ? ? ma ma configuration of footnote. a smp trip voltage is set to 3.25v. smp trip voltage is set to 5.0v. v bat 5v input voltage range from battery 1.8 ? 5.0 v configuration of footnote. a smp trip voltage is set to 5.0v. v bat 3v input voltage range from battery 1.0 ? 3.3 v configuration of footnote. a smp trip voltage is set to 3.25v. v batstart minimum input voltage from battery to start pump 1.2 ? ? v configuration of footnote. a 0 o c t a 100. 1.25v at t a = -40 o c. v pump_line line regulation (over v bat range) ? 5 ? %v o configuration of footnote. a v o is the ?vdd value for pump trip? specified by the vm[2:0] setting in the dc por a nd lvd specification, table 3-15 on page 27. v pump_loa d load regulation ? 5 ? %v o configuration of footnote. a v o is the ?vdd value for pump trip? specified by the vm[2:0] setting in the dc por a nd lvd specification, table 3-15 on page 27. v pump_rip ple output voltage ripple (depends on capacitor/load) ? 100 ? mvpp configuration of footnote. a load is 5 ma. e 3 efficiency 35 50 ? % configuration of footnote. a load is 5 ma. smp trip voltage is set to 3.25v.
cy8cled16 document number: 001-13105 rev. ** page 21 of 39 figure 5. basic switch mode pump circuit dc analog reference specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. the guaranteed specifications ar e measured through the analog continuous time psoc blocks. the power levels for agnd refer to the power of the analog c ontinuous time psoc block. the power levels for refhi and reflo refer to the analog reference control register. the limits st ated for agnd include the offset error of the agnd buffer local to the analog continuous time psoc block. reference control power is high. f pump switching frequency ? 1.4 ? mhz dc pump switching duty cycle ? 50 ? % a. l 1 = 2 h inductor, c 1 = 10 f capacitor, d 1 = schottky diode. see figure 5. table 17. dc switch mode pump (smp) specifications (continued) battery c1 d1 + psoc vdd vss smp v bat v pump l 1 table 18. 5v dc analog reference specifications symbol description min typ max units v bg5 bandgap voltage reference 5v 1.28 1.30 1.32 v ? agnd = vdd/2 a vdd/2 - 0.02 vdd/2 vdd/2 + 0.02 v ? agnd = 2 x bandgap a 2.52 2.60 2.72 v ? agnd = p2[4] (p2[4] = vdd/2) a p2[4] - 0.013 p2[4] p2[4] + 0.013 v ? agnd = bandgap a 1.27 1.3 1.34 v ? agnd = 1.6 x bandgap a 2.03 2.08 2.13 v ? agnd block to block variation (agnd = vdd/2) a -0.034 0.000 0.034 v ? refhi = vdd/2 + bandgap vdd /2 + 1.21 vdd /2 + 1.3 vdd /2 + 1.382 v ? refhi = 3 x bandgap 3.75 3.9 4.05 v ? refhi = 2 x bandgap + p2[6] (p2[6] = 1.3v) p2[6] + 2.478 p2[6] + 2.6 p2[6] + 2.722 v ? refhi = p2[4] + bandgap (p2[4] = vdd/2) p2[4] + 1.218 p2[4] + 1.3 p2[4] + 1.382 v ? refhi = p2[4] + p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) p2[4] + p2[6] - 0.058 p2[4] + p2[6] p2[4] + p2[6] + 0.058 v ? refhi = 2 x bandgap 2.50 2.60 2.70 v ? refhi = 3.2 x bandgap 4.02 4.16 4.29 v ? reflo = vdd/2 ? bandgap vdd /2 - 1.369 vdd /2 - 1.30 vdd /2 - 1.231 v ? reflo = bandgap 1.20 1.30 1.40 v ? reflo = 2 x bandgap - p2[6] (p2[6] = 1.3v) 2.489 - p2[6] 2.6 - p2[6] 2.711 - p2[6] v ? reflo = p2[4] ? bandgap (p2[4] = vdd/2) p2[4] - 1.368 p2[4] - 1.30 p2[4] - 1.232 v ? reflo = p2[4]-p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) p2[4] - p2[6] - 0.042 p2[4] - p2[6] p2[4] - p2[6] + 0.042 v a. agnd tolerance includes the offsets of the local buffer in the psoc block. bandgap voltage is 1.3v 0.02v.
cy8cled16 document number: 001-13105 rev. ** page 22 of 39 dc analog psoc block specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 19. 3.3v dc analog reference specifications symbol description min typ max units v bg33 bandgap voltage reference 3.3v 1.28 1.30 1.32 v ? agnd = vdd/2 a vdd/2 - 0.02 vdd/2 vdd/2 + 0.02 v ? agnd = 2 x bandgap a not allowed ? agnd = p2[4] (p2[4] = vdd/2) p2[4] - 0.009 p2[4] p2[4] + 0.009 v ? agnd = bandgap a 1.27 1.30 1.34 v ? agnd = 1.6 x bandgap a 2.03 2.08 2.13 v ? agnd block to block variation (agnd = vdd/2) a -0.034 0.000 0.034 mv ? refhi = vdd/2 + bandgap not allowed ? refhi = 3 x bandgap not allowed ? refhi = 2 x bandgap + p2[6] (p2[6] = 0.5v) not allowed ? refhi = p2[4] + bandgap (p2[4] = vdd/2) not allowed ? refhi = p2[4] + p2[6] (p2[4] = vdd/2, p2[6] = 0.5v) p2[4] + p2[6] - 0.042 p2[4] + p2[6] p2[4] + p2[6] + 0.042 v ? refhi = 2 x bandgap 2.50 2.60 2.70 v ? refhi = 3.2 x bandgap not allowed ? reflo = vdd/2 - bandgap not allowed ? reflo = bandgap not allowed ? reflo = 2 x bandgap - p2[6] (p2[6] = 0.5v) not allowed ? reflo = p2[4] ? bandgap (p2[4] = vdd/2) not allowed ? reflo = p2[4]-p2[6] (p2[4] = vdd/2, p2[6] = 0.5v) p2[4] - p2[6] - 0.036 p2[4] - p2[6] p2[4] - p2[6] + 0.036 v a. agnd tolerance includes the offsets of the local buffer in the psoc block. bandgap voltage is 1.3v 0.02v. table 20. dc analog psoc block specifications symbol description min typ max units notes r ct resistor unit value (continuous time) ? 12.2 ? k c sc capacitor unit value (switch cap) ? 80 ? ff
cy8cled16 document number: 001-13105 rev. ** page 23 of 39 dc por, smp, and lvd specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 21. dc por, smp, and lvd specifications symbol description min typ max units notes v ppor0r v ppor1r v ppor2r vdd value for ppor trip (positive ramp) porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.91 4.39 4.55 ? v v v v ppor0 v ppor1 v ppor2 vdd value for ppor trip (negative ramp) porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.82 4.39 4.55 ? v v v v ph0 v ph1 v ph2 ppor hysteresis porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? ? ? 92 0 0 ? ? ? mv mv mv v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 vdd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 2.98 a 3.08 3.20 4.08 4.57 4.74 b 4.82 4.91 a. always greater than 50 mv above ppor (porlev = 00) for falling supply. b. always greater than 50 mv above ppor (porlev = 10) for falling supply. v v v v v v v v v v pump0 v pump1 v pump2 v pump3 v pump4 v pump5 v pump6 v pump7 vdd value for smp trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.96 3.03 3.18 4.11 4.55 4.63 4.72 4.90 3.02 3.10 3.25 4.19 4.64 4.73 4.82 5.00 3.08 3.16 3.32 4.28 4.74 4.82 4.91 5.10 v v v v v v v v v
cy8cled16 document number: 001-13105 rev. ** page 24 of 39 dc programming specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 22. dc programming specifications symbol description min typ max units notes i ddp supply current during programming or verify ? 10 30 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.2 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] dur- ing programming or verify ? ? 0.2 ma driving internal pull-down resistor. i ihp input current when applying vihp to p1[0] or p1[1] dur- ing programming or verify ? ? 1.5 ma driving internal pull-down resistor. v olv output low voltage during programming or verify ? ? vss + 0.75 v v ohv output high voltage during programming or verify vdd - 1.0 ? vdd v flash enpb flash endurance (per block) 50,000 ? ? ? erase/write cycles per block. flash ent flash endurance (total) a a. a maximum of 36 x 50,000 block endurance cycles is allowed. this may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). for the full industrial range, the user must employ a temperatur e sensor user module (flashtemp) and feed the result to the tem perature argument before writing. refer to the flash apis application note an2015 at http://www.cyp ress.com under application notes for more information. 1,800,00 0 ? ? ? erase/write cycles. flash dr flash data retention 10 ? ? years
cy8cled16 document number: 001-13105 rev. ** page 25 of 39 ac electrical characteristics ac chip-level specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. note see the individual user module data sheets for information on maximum frequencies for user modules. table 23. ac chip-level specifications symbol description min typ max units notes f imo24 internal main oscillator frequency for 24 mhz 23.4 24 24.6 a,b,c mhz trimmed for 5v or 3.3v operation using factory trim values. see the figure on page 19. slimo mode = 0. f imo6 internal main oscillator frequency for 6 mhz 5.75 6 6.35 a,b,c mhz trimmed for 5v or 3.3v operation using factory trim values. see the figure on page 19. slimo mode = 1. f cpu1 cpu frequency (5v nominal) 0.93 24 24.6 a,b a. 4.75v < vdd < 5.25v. b. accuracy derived from internal main osci llator with appropriate trim for vdd range. mhz f cpu2 cpu frequency (3.3v nominal) 0.93 12 12.3 b, c c. 3.0v < vdd < 3.6v. see application note an2012 ?adjusting psoc microcontroller trims for dual voltage-range operation? for in formation on trimming for operation at 3.3v. mhz f 48m digital psoc block frequency 0 48 49.2 a,b,d d. see the individual user module data sheets for in formation on maximum frequencies for user modules. mhz refer to the ac digital block specifications below. f 24m digital psoc block frequency 0 24 24.6 b, d mhz f 32k1 internal low speed oscillator frequency 15 32 64 khz f 32k2 external crystal oscillator ? 32.768 ? khz accuracy is capacitor and crystal dependent. 50% duty cycle. f pll pll frequency ? 23.986 ? mhz a multiple (x732) of crystal frequency. jitter24m2 24 mhz period jitter (pll) ? ? 600 ps t pllslew pll lock time 0.5 ? 10 ms t pllslewlow pll lock time for low gain setting 0.5 ? 50 ms t os external crystal oscillator startup to 1% ? 250 500 ms t osacc external crystal oscillator startup to 100 ppm ? 300 600 ms the crystal oscillator frequency is within 100 ppm of its final value by the end of the t osacc period. correct opera- tion assumes a properly loaded 1 uw maximum drive level 32.768 khz crystal. 3.0v vdd 5.5v, -40 o c t a 85 o c. jitter32k 32 khz period jitter ? 100 ns t xrst external reset pulse width 10 ? ? s dc24m 24 mhz duty cycle 40 50 60 % step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 46.8 48.0 49.2 a,c mhz trimmed. utilizing factory trim values. jitter24m1 24 mhz period jitter (imo) ? 600 ps f max maximum frequency of signal on row input or row out- put. ? ? 12.3 mhz t ramp supply ramp time 0 ? ? s
cy8cled16 document number: 001-13105 rev. ** page 26 of 39 figure 6. pll lock timing diagram figure 7. pll lock for low gain setting timing diagram figure 8. external crystal o scillator startup timing diagram figure 9. 24 mhz period jitter (imo) timing diagram figure 10. 32 khz period jitter (eco) timing diagram 24 mhz f pll pll enable t pllslew pll gain 0 24 mhz f pll pll enable t pllslewlow pll gain 1 32 khz f 32k2 32k select t os jitter24m1 f 24m jitter32k f 32k2
cy8cled16 document number: 001-13105 rev. ** page 27 of 39 ac general purpose io specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. figure 11. gpio timing diagram ac operational amplifier specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. settling times, slew rates, and gain bandwidth are based on the analog continuous time psoc block. power = high and opamp bias = high is not supported at 3.3v. table 24. ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12.3 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns vdd = 4.75 to 5.25v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns vdd = 4.75 to 5.25v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 10 27 ? ns vdd = 3 to 5.25v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 10 22 ? ns vdd = 3 to 5.25v, 10% - 90% tfallf tfalls trisef trises 90% 10% gpio pin output voltage
cy8cled16 document number: 001-13105 rev. ** page 28 of 39 table 25. 5v ac operatio nal amplifier specifications symbol description min typ max units notes t roa rising settling time to 0.1% for a 1v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 3.9 0.72 0.62 s s s t soa falling settling time to 0.1% for a 1v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 5.9 0.92 0.72 s s s sr roa rising slew rate (20% to 80%) of a 1v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.15 1.7 6.5 ? ? ? ? ? ? v/ s v/ s v/ s sr foa falling slew rate (20% to 80%) of a 1v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.01 0.5 4.0 ? ? ? ? ? ? v/ s v/ s v/ s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.75 3.1 5.4 ? ? ? ? ? ? mhz mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz table 26. 3.3v ac operational amplifier specifications symbol description min typ max units notes t roa rising settling time to 0.1% of a 1v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 3.92 0.72 s s t soa falling settling time to 0.1% of a 1v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 5.41 0.72 s s sr roa rising slew rate (20% to 80%) of a 1v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.31 2.7 ? ? ? ? v/ s v/ s sr foa falling slew rate (20% to 80%) of a 1v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.24 1.8 ? ? ? ? v/ s v/ s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high 0.67 2.8 ? ? ? ? mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz
cy8cled16 document number: 001-13105 rev. ** page 29 of 39 when bypassed by a capacitor on p2[4], the noise of the analog gr ound signal distributed to each block is reduced by a factor o f up to 5 (14 db). this is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacit or. figure 12. typical agnd noise with p2[4] bypass at low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. at high frequencies, increased power level reduces the noise spectrum level. figure 13. typical opamp noise ac low power comparator specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v at 25 c and are for design guidance only. 100 1000 10000 0.001 0.01 0.1 1 10 100 fr eq ( khz ) dbv/rthz 0 0.01 0.1 1.0 10 10 100 1000 10000 0.001 0.01 0.1 1 10 100 freq (khz) nv/rthz ph_ bh ph_ bl pm_bl pl_ bl table 27. ac low power comparator specifications symbol description min typ max units notes t rlpc lpc response time ? ? 50 s 50 mv overdrive comparator reference set within v reflpc .
cy8cled16 document number: 001-13105 rev. ** page 30 of 39 ac digital block specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 28. ac digital block specifications function description min typ max units notes all functions maximum block clocking frequency (> 4.75v) 49.2 mhz 4.75v < vdd < 5.25v. maximum block clocking frequency (< 4.75v) 24.6 mhz 3.0v < vdd < 4.75v. timer capture pulse width 50 a a. 50 ns minimum input pulse width is based on the input sy nchronizers running at 24 mh z (42 ns nominal period). ? ? ns maximum frequency, no capture ? ? 49.2 mhz 4.75v < vdd < 5.25v. maximum frequency, with capture ? ? 24.6 mhz counter enable pulse width 50 a ? ? ns maximum frequency, no enable input ? ? 49.2 mhz 4.75v < vdd < 5.25v. maximum frequency, enable input ? ? 24.6 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 50 a ? ? ns disable mode 50 a ? ? ns maximum frequency ? ? 49.2 mhz 4.75v < vdd < 5.25v. crcprs (prs mode) maximum input clock frequency ? ? 49.2 mhz 4.75v < vdd < 5.25v. crcprs (crc mode) maximum input clock frequency ? ? 24.6 mhz spim maximum input clock frequency ? ? 8.2 mhz maximum data rate at 4.1 mhz due to 2 x over clocking. spis maximum input clock frequency ? ? 4.1 ns width of ss_ negated between transmissions 50 a ? ? ns transmitter maximum input clock frequency vdd 4.75v, 2 stop bits ? ? ? ? 24.6 49.2 mhz mhz maximum data rate at 3.08 mhz due to 8 x over clocking. maximum data rate at 6.15 mhz due to 8 x over clocking. receiver maximum input clock frequency vdd 4.75v, 2 stop bits ? ? ? ? 24.6 49.2 mhz mhz maximum data rate at 3.08 mhz due to 8 x over clocking. maximum data rate at 6.15 mhz due to 8 x over clocking.
cy8cled16 document number: 001-13105 rev. ** page 31 of 39 ac analog output buffer specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 29. 5v ac analog ou tput buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 4 4 s s t sob falling settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 3.4 3.4 s s sr rob rising slew rate (20% to 80%), 1v step, 100pf load power = low power = high 0.5 0.5 ? ? ? ? v/ s v/ s sr fob falling slew rate (80% to 20%), 1v step, 100pf load power = low power = high 0.55 0.55 ? ? ? ? v/ s v/ s bw ob small signal bandwidth, 20mv pp , 3db bw, 100pf load power = low power = high 0.8 0.8 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1v pp , 3db bw, 100pf load power = low power = high 300 300 ? ? ? ? khz khz table 30. 3.3v ac analog ou tput buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 4.7 4.7 s s t sob falling settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 4 4 s s sr rob rising slew rate (20% to 80%), 1v step, 100pf load power = low power = high .36 .36 ? ? ? ? v/ s v/ s sr fob falling slew rate (80% to 20%), 1v step, 100pf load power = low power = high .4 .4 ? ? ? ? v/ s v/ s bw ob small signal bandwidth, 20mv pp , 3db bw, 100pf load power = low power = high 0.7 0.7 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1v pp , 3db bw, 100pf load power = low power = high 200 200 ? ? ? ? khz khz
cy8cled16 document number: 001-13105 rev. ** page 32 of 39 ac external clock specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temp erature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. ac programming specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. table 31. 5v ac external clock specifications symbol description min typ max units notes f oscext frequency 0.093 ? 24.6 mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power up imo to switch 150 ? ? s table 32. 3.3v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.093 ? 12.3 mhz maximum cpu frequency is 12 mhz at 3.3v. with the cpu clock divider set to 1, the exter- nal clock must adhere to the maximum fre- quency and duty cycle requirements. f oscext frequency with cpu clock divide by 2 or greater 0.186 ? 24.6 mhz if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider will ensure that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power up imo to switch 150 ? ? s table 33. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 10 ? ms t write flash block write time ? 10 ? ms t dsclk data out delay from falling edge of sclk ? ? 45 ns vdd > 3.6 t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 vdd 3.6
cy8cled16 document number: 001-13105 rev. ** page 33 of 39 ac i 2 c specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c and are for design guidance only. figure 14. definition for timing for fast/standard mode on the i 2 c bus table 34. ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c set-up time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data set-up time 250 ? 100 a a. a fast-mode i2c-bus device can be used in a standard-mode i2c-bus system, but the requirement t su;dat 250 ns must then be met. this w ill automatically be the case if the device does not stretch the low period of the scl signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i2 c-bus specification) before the scl line is released. ?ns t sustoi2c set-up time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ?050ns sda scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c
cy8cled16 document number: 001-13105 rev. ** page 34 of 39 packaging information this section illustrates the packaging spec ifications for the cy8cled16 ez-color dev ice, along with the thermal impedances for each package and the typical package capacitance on crystal pins. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a detailed description of the emulation tools? dimensions, refer to the document titled psoc emulator pod dimensions at http://www.cypress. com/design/mr10161 . packaging dimensions figure 15. 28-lead (210-mil) ssop figure 16. 48-lead (300-mil) ssop 51-85079 *c 51-85061- c 51-85061 *c
cy8cled16 document number: 001-13105 rev. ** page 35 of 39 figure 17. 48-lead (7x7 mm) qfn important note for information on the preferred dimensions for mount ing qfn packages, see the following application note at http://www.amkor.com/products/notes_papers/mlfappnote.pdf . important note pinned vias for thermal conduction are not required for the low-power psoc device. 001-12919 *a
cy8cled16 document number: 001-13105 rev. ** page 36 of 39 thermal impedances capacitance on crystal pins solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. development tool selection software this section presents the development tools available for all current psoc device families including the cy8cled16 ez-color family. psoc express ? as the newest addition to the psoc development software suite, psoc express is the first visual embedded system design tool that allows a user to create an entire psoc project and generate a schematic, bom, and data sh eet without writing a single line of code. users work directly with application objects such as leds, switches, sensors, and f ans. psoc express is available free of charge at http: //www.cypress.com/psocexpress. psoc designer ? at the core of the psoc development software suite is psoc designer. utilized by thousands of psoc developers, this robust software has been facilitating psoc designs for half a decade. psoc designer is available free of charge at http://www.cypress.com/psocdesigner . psoc programmer flexible enough to be used on the bench in development, yet suitable for factory progra mming, psoc programmer works either as a standalone programming application or it can operate directly from psoc designer or psoc express. psoc programmer software is compatible with both psoc ice-cube in-circuit emulator and psoc miniprog. psoc programmer is available free of charge at http://www.cypre ss.com/psocpro- grammer. cy3202-c imagecraft c compiler cy3202 is the optional upgrade to psoc designer that enables the imagecraft c compiler. it can be purchased from the cypress online store. at http://www.cypress.com , click the online store shopping cart icon at the bottom of the web page, and click psoc (programmable system-on-chip) to view a current list of available items. evaluation tools all evaluation tools can be purchased from the cypress online store. cy3261a-rgb ez-color rgb kit the cy3261a-rgb board is a preprogrammed hb led color mix board with seven pre-set colors using the cy8cled16 ez-color hb led controller. the board is accompanied by a cd containing the color selector software application, psoc express 3.0 beta 2, psoc programmer, and a suite of documents, schematics, and firmware examples. the color selector software application can be installed on a host pc and is used to control the ez-color hb led controller using the included usb cable. the application enables you to select colors via a cie 1931 chart or by enterin g coordinates. the kit includes: training board (cy8cled16) one mini-a to mini-b usb cable psoc express cd-rom design files and application installation cd-rom to program and tune this kit via psoc express 3.0 you must use a mini programmer unit (cy3217 kit) and a cy3240-i2cusb kit. table 35. thermal impedances per package package typical ja * 28 ssop 94 o c/w 48 ssop 69 o c/w 48 qfn** 28 o c/w * t j = t a + power x ja ** to achieve the thermal impedance specified for the qfn package, the center thermal pad should be soldered to the pcb ground plane. table 36. typical package capacitance on crystal pins package package capacitance 28 ssop 2.8 pf 48 ssop 3.3 pf 48 qfn 1.8 pf table 37. solder reflow peak temperature package minimum peak temperature* maximum peak temperature 28 ssop 240 o c 260 o c 48 ssop 220 o c 260 o c 48 qfn 220 o c 260 o c *higher temperatures may be required based on the solder melting point. typical temperatures for solder are 220 5 o c with sn-pb or 245 5 o c with sn-ag-cu paste. refer to the solder manufacturer specifications.
cy8cled16 document number: 001-13105 rev. ** page 37 of 39 cy3210-miniprog1 the cy3210-miniprog1 kit allows a user to program psoc devices via the miniprog1 programming unit. the miniprog is a small, compact prototyping programmer that connects to the pc via a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466-24pxi pdip psoc device sample 28-pin cy8c27443-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiometer, leds, and plenty of bread- boarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit 28-pin cy8c29466-24pxi pdip psoc device sample (2) psoc designer software cd getting started guide usb 2.0 cable device programmers all device programmers can be purchased from the cypress online store. cy3216 modular programmer the cy3216 modular programmer kit features a modular programmer and the miniprog1 programming unit. the modular programmer includes three programming module cards and supports multiple cypress products. the kit includes: modular programmer base 3 programming module cards miniprog programming unit psoc designer software cd getting started guide usb 2.0 cable cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industrial case that is more robust than the miniprog in a production-programming environment. note : cy3207issp needs special software and is not compatible with psoc programmer. the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240v power supply, euro-plug adapter usb 2.0 cable accessories (emulation and programming) 3rd-party tools several tools have been specially designed by the following 3rd-party vendors to accompany psoc devices during devel- opment and production. specific details for each of these tools can be found at http://www.cypress.com under design resources >> evaluation boards. build a psoc emulator into your board for details on how to emulate your circuit before going to volume production using an on-chip debug (ocd) non-production psoc device, see application note ?debugging - build a psoc emulator into your board - an2323? at http://www.cypre ss.com/an2323 . table 38. emulation and programming accessories part # pin package flex-pod kit a a. flex-pod kit includes a practice flex-pod and a practice pcb, in addition to two flex-pods. foot kit b b. foot kit includes surface mount feet that can be soldered to the target pcb. adapter c c. programming adapter converts non-dip package to dip footprint. specific details and ordering information for each of the adapters can be found at http://www.emulation.com . cy8cled16- 28pvxi 28 ssop cy3250-29xxx cy3250-28 ssop-fk adapters can be found at http://www.emu- lation.com . cy8cled16- 48pvxi 48 ssop cy3250-29xxx cy3250-48 ssop-fk cy8cled16- 48lfxi 48 qfn cy3250-29xxx qfn cy3250-48 qfn-fk
cy8cled16 document number: 001-13105 rev. ** page 38 of 39 ordering information key device features the following table lists the cy8cled16 ez-color de vices? key package features and ordering codes. ordering code definitions table 39. device key features and ordering information package ordering code flash (bytes) ram (bytes) switch mode pump temperature range digital psoc blocks analog psoc blocks digital io pins analog inputs analog outputs xres pin 28 pin (210 mil) ssop CY8CLED16-28PVXI 32k 2k yes -40c to +85c 16 12 24 12 4 yes 28 pin (210 mil) ssop (tape and reel) CY8CLED16-28PVXIt 32k 2k yes -40c to +85c 16 12 24 12 4 yes 48 pin (300 mil) ssop cy8cled16-48pvxi 32k 2k yes -40c to +85c 16 12 44 12 4 yes 48 pin (300 mil) ssop (tape and reel) cy8cled16-48pvxit 32k 2k yes -40c to +85c 16 12 44 12 4 yes 48 pin qfn cy8cled16-48lfxi 32k 2k yes -40c to +85c 16 12 44 12 4 yes 48 pin qfn (tape and reel) cy8cled16-48lfxit 32k 2k yes -40c to +85c 16 12 44 12 4 yes cy 8 c led xx - xx xxxx package type: thermal rating: px = pdip pb-free c = commercial sx = soic pb-free i = industrial pvx = ssop pb-free e = extended lfx/lkx = qfn pb-free ax = tqfp pb-free pin count part number led family code technology code: c = cmos marketing code: 8 = cypress psoc company id: cy = cypress
cy8cled16 document number: 001-13105 rev. ** page 39 of 39 document history table 40. cy8cled16 data sheet revision history document title: cy8cled16 ez-color hb led controller document number: 001-13105 revision ecn # issue date origin of change description of change ** 1148504 see ecn sfvtmp3 new document (revision **). distribution : external/public posting : none ? cypress semiconductor corporation, 2007. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunct ion or failure may reasonably be expected to result in signi ficant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufact urer assumes all risk of such use and in doing so indemnifies cypress against all charges. psoc designer?, programmable system-on-chip?, and psoc express? are trademarks and psoc? is a registered trademark of cypress s emiconductor corp. all other trademarks or registered trademarks referenced herein are property of the respective corporations. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware i n support of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation , or representation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or impl ied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress re serves the right to make change s without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of an y product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress ' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement.

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